The Intel Xeon Phi is the first commercially available product of the Intel MIC architecture. It was codenamed Intel Knights Corner (KNC) and is the successor of Knights Ferry (KNF). It has 60 (or 61) cores and runs at a fixed clock speed of 1.053 GHz. It contains 8 GB of GDDR5 random access memory with a bandwidth of 320 GB/s. On the cache side we have 32KB for instructions and 32KB for data in L1 (each 8-way, with 64B line size). The L2 consist of 512KB slices per core, but can also be thought of as a fully coherent cache, with a total size equal to the sum of the slices. Information can be copied to each core that uses it to provide the fastest possible local access, or a single copy can be present for all cores to provide maximum cache capacity. The L2 cache contains both instructions and data (again 8-way and 64B line size).
I am currently involved in research on threading, especially barriers and synchronization, with the Xeon phi. Some of my results will be published here along with links to articles in the Intel Developer Zone and related publications.